The vast majority of Integrated circuits (IC) are fabricated with traditional crystalline silicon CMOS technology (“CMOS”). Unless otherwise noted specifically, CMOS refers herein to traditional crystalline silicon transistors found in the vast majority of today's integrated circuit devices fabricated in semiconductor fabs where high temperature (>450 C) front end equipment is required. As ICs continue to scale to smaller geometries RC time delays in the interconnects (wiring on the chips) becomes a major design issue hampering further improvements in performance normally expected with improved scalability of the production process to smaller technology nodes. Three dimensional (3D) integrated circuits are expected to be the next stage in the evolution of ICs, however, 3D circuit fabrication with conventional CMOS technology is not possible. Much is discussed in the industry about “3D”, but all relate to stacking of die or circuits in one form of another requiring complex interposers and manufacturing methods. New methods are needed to develop 3D circuits in a monolithic fashion which incorporates memory, logic, IO and other elements and features that increase performance (speed and density), at low power consumption and low cost.
Nonvolatile crosspoint memory technologies such as resistance random access memory (ReRAM or RRAM), conductive bridge RAM (CBRAM), phase change random access memory (PCM or PCRAM), Nano-RAM carbon nanotube based memory (NRAM), and magnetic random access memory (MRAM) using magnetic tunnel junctions (MTJs) are strong candidates for providing a dense and fast nonvolatile storage solution for future memory applications. The ability of MRAM, RRAM, NRAM and PCRAM to more effectively compete with established memory types, such as dynamic random access memory (DRAM), static random access memory (SRAM) and FLASH memory (NAND or NOR) can be maximized by increasing the density at which memory units (a memory cell and its associated driving circuits) can be formed on a chip.
A crosspoint memory (also referred at times as a crossbar memory) is common terminology in the semiconductor memory industry and is herein further defined to be a memory array disposed on or above the substrate surface, arranged in a matrix and comprising a plurality of parallel first conductive lines, a plurality of parallel second conductive lines overlapping the first conductive lines at a plurality of intersection regions, a plurality of memory cells, each memory cell being disposed at an intersection region of the conductive lines, electrically coupled to one of the first conductive lines at a first terminal and to one of the second conductive lines at a second terminal, and comprising a controllable electrical resistance.
A conventional MTJ includes at least a pinned ferromagnetic layer and a free ferromagnetic layer separated from each other by a thin tunnel barrier layer. The free layer has a reversible magnetization direction that can have two stable directions that are parallel or anti-parallel to a fixed magnetization direction of the pinned layer. Resistance of the MTJ depends on the mutual orientation of the magnetizations in the free and pinned layers and can be effectively controlled.
A typical MRAM device includes an array of memory cells, a plurality of parallel word lines extended along columns (or rows) of the memory cells, and a plurality of parallel bit lines extended along rows (or columns) of the memory cells. The word and bit lines overlay each other but spaced from each other in a vertical direction. Each memory cell is located at a crosspoint of a word line and a bit line, and typically includes a single MTJ connected in series with a selection metal-oxide-semiconductor (MOS) transistor. The connected in series MTJ and transistor are electrically coupled to the word line at one terminal and to the bit line at the opposite terminal.
FIG. 1 shows a circuit diagram for a magnetic random access memory (MRAM) array according to a prior art disclosed in U.S. patent application publication US 2012/0281465. U.S. patent application publication US 2012/0281465 discloses in detail various methods of writing bits (“0” and “1”) to the memory cells as well as reading and erasing the bits. The disclosure of US 2012/0281465 is hereby incorporated herein in its entirety by reference.
FIG. 2 shows a cross sectional view of a magnetic memory cell made with magnetic materials having perpendicular anisotropy according to the prior art.
The circuit described by US 2012/0281465 presents a challenge to controlling the addressing of the memory array for writing, reading or erasing due to the fact alternative current paths are possible than those described in the disclosure. This problem is also described in U.S. Pat. Nos. 7,968,419 and 8,227,788, which teach the use of back to back Schottky diodes in a resistance memory array to solve the cross talk problems associated when reading from the array. FIG. 3A is a circuit diagram of a crosspoint resistance nonvolatile memory array including resistance variable elements 105 with back to back Schottky diodes (referred to as current controlling elements) 112 according to U.S. Pat. No. 8,227,788. Word and bit conductive lines are indicated at 101 and 119.
US 2012/0281465 describes location of the selection transistors positioned along the perimeter of the array which still requires valuable die area. The use of MOS transistors (in particular silicon based Complimentary Metal Oxide Semiconductor—CMOS) as a selection element limits the arrangement of the existing MRAM into three-dimensional configuration due to long interconnects to the selection transistor from the remote layers of MTJs. Moreover, the MOS technology is relatively expensive.
An improved method of fabricating and addressing the word and bit selection transistors in nonvolatile memory arrays, such as MRAM memory arrays, is required that retains the advantages of small die size due to the crosspoint design of the memory array and eliminates the MOS transistors altogether to enable lower cost.
The present application addresses the above problems and provides a solution for low cost three-dimensional (3D) integrated circuits including nonvolatile crosspoint memory arrays. The solutions provided by the disclosures herein also addresses improved methods of fabricating 3D integrated circuits including memory, logic and other functions. The 3D devices described herein provide a much simpler approach to 3D compared to the conventional “3D” approaches under development in the semiconductor industry as of this writing—i.e., stacked die, package on package (PoP) and through silicon via (TSV) techniques which require costly and complex interconnect processes such as silicon interposers.